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#define | PROCESSOR_ARCHITECTURE_INTEL 0 |
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#define | PROCESSOR_ARCHITECTURE_MIPS 1 |
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#define | PROCESSOR_ARCHITECTURE_ALPHA 2 |
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#define | PROCESSOR_ARCHITECTURE_PPC 3 |
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#define | PROCESSOR_ARCHITECTURE_SHX 4 |
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#define | PROCESSOR_ARCHITECTURE_ARM 5 |
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#define | PROCESSOR_ARCHITECTURE_IA64 6 |
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#define | PROCESSOR_ARCHITECTURE_ALPHA64 7 |
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#define | PROCESSOR_ARCHITECTURE_MSIL 8 |
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#define | PROCESSOR_ARCHITECTURE_AMD64 9 |
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#define | PROCESSOR_ARCHITECTURE_IA32_ON_WIN64 10 |
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#define | PROCESSOR_ARCHITECTURE_NEUTRAL 11 |
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#define | PROCESSOR_ARCHITECTURE_ARM64 12 |
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#define | PROCESSOR_ARCHITECTURE_MIPS64 13 |
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#define | PROCESSOR_ARCHITECTURE_E2K 14 |
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#define | PROCESSOR_ARCHITECTURE_UNKNOWN 0xFFFF |
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#define | PROCESSOR_INTEL_386 386 |
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#define | PROCESSOR_INTEL_486 486 |
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#define | PROCESSOR_INTEL_PENTIUM 586 |
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#define | PROCESSOR_INTEL_IA64 2200 |
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#define | PROCESSOR_AMD_X8664 8664 |
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#define | PROCESSOR_MIPS_R4000 4000 |
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#define | PROCESSOR_ALPHA_21064 21064 |
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#define | PROCESSOR_PPC_601 601 |
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#define | PROCESSOR_PPC_603 603 |
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#define | PROCESSOR_PPC_604 604 |
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#define | PROCESSOR_PPC_620 620 |
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#define | PROCESSOR_HITACHI_SH3 10003 |
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#define | PROCESSOR_HITACHI_SH3E 10004 |
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#define | PROCESSOR_HITACHI_SH4 10005 |
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#define | PROCESSOR_MOTOROLA_821 821 |
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#define | PROCESSOR_SHx_SH3 103 |
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#define | PROCESSOR_SHx_SH4 104 |
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#define | PROCESSOR_STRONGARM 2577 |
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#define | PROCESSOR_ARM720 1824 |
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#define | PROCESSOR_ARM820 2080 |
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#define | PROCESSOR_ARM920 2336 |
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#define | PROCESSOR_ARM_7TDMI 70001 |
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#define | PROCESSOR_OPTIL 0x494F |
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#define | VER_NT_DOMAIN_CONTROLLER 0x0000002 |
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#define | VER_NT_SERVER 0x0000003 |
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#define | VER_NT_WORKSTATION 0x0000001 |
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#define | PF_FLOATING_POINT_PRECISION_ERRATA 0 |
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#define | PF_FLOATING_POINT_EMULATED 1 |
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#define | PF_COMPARE_EXCHANGE_DOUBLE 2 |
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#define | PF_MMX_INSTRUCTIONS_AVAILABLE 3 |
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#define | PF_PPC_MOVEMEM_64BIT_OK 4 |
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#define | PF_XMMI_INSTRUCTIONS_AVAILABLE 6 /* SSE */ |
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#define | PF_3DNOW_INSTRUCTIONS_AVAILABLE 7 |
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#define | PF_RDTSC_INSTRUCTION_AVAILABLE 8 |
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#define | PF_PAE_ENABLED 9 |
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#define | PF_XMMI64_INSTRUCTIONS_AVAILABLE 10 /* SSE2 */ |
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#define | PF_SSE_DAZ_MODE_AVAILABLE 11 |
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#define | PF_NX_ENABLED 12 |
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#define | PF_SSE3_INSTRUCTIONS_AVAILABLE 13 |
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#define | PF_COMPARE_EXCHANGE128 14 |
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#define | PF_COMPARE64_EXCHANGE128 15 |
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#define | PF_CHANNELS_ENABLED 16 |
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#define | PF_XSAVE_ENABLED 17 |
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#define | PF_ARM_VFP_32_REGISTERS_AVAILABLE 18 |
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#define | PF_ARM_NEON_INSTRUCTIONS_AVAILABLE 19 |
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#define | PF_SECOND_LEVEL_ADDRESS_TRANSLATION 20 |
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#define | PF_VIRT_FIRMWARE_ENABLED 21 |
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#define | PF_RDWRFSGSBASE_AVAILABLE 22 |
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#define | PF_FASTFAIL_AVAILABLE 23 |
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#define | PF_ARM_DIVIDE_INSTRUCTION_AVAILABLE 24 |
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#define | PF_ARM_64BIT_LOADSTORE_ATOMIC 25 |
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#define | PF_ARM_EXTERNAL_CACHE_AVAILABLE 26 |
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#define | PF_ARM_FMAC_INSTRUCTIONS_AVAILABLE 27 |
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#define | PF_SSSE3_INSTRUCTIONS_AVAILABLE 36 |
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#define | PF_SSE4_1_INSTRUCTIONS_AVAILABLE 37 |
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#define | PF_SSE4_2_INSTRUCTIONS_AVAILABLE 38 |
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#define | PF_AVX_INSTRUCTIONS_AVAILABLE 39 |
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#define | PF_AVX2_INSTRUCTIONS_AVAILABLE 40 |
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#define | PF_AVX512F_INSTRUCTIONS_AVAILABLE 41 |
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#define | PF_ARM_V8_INSTRUCTIONS_AVAILABLE 29 |
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#define | PF_ARM_V8_CRYPTO_INSTRUCTIONS_AVAILABLE 30 |
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#define | PF_ARM_V8_CRC32_INSTRUCTIONS_AVAILABLE 31 |
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#define | PF_ARM_V81_ATOMIC_INSTRUCTIONS_AVAILABLE 34 |
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#define | PF_ARM_V82_DP_INSTRUCTIONS_AVAILABLE 43 |
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#define | PF_ARM_V83_JSCVT_INSTRUCTIONS_AVAILABLE 44 |
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#define | PF_ARM_V83_LRCPC_INSTRUCTIONS_AVAILABLE 45 |
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#define | PF_ARM_V4 0x80000001 |
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#define | PF_ARM_V5 0x80000002 |
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#define | PF_ARM_V6 0x80000003 |
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#define | PF_ARM_V7 0x80000004 |
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#define | PF_ARM_THUMB 0x80000005 |
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#define | PF_ARM_JAZELLE 0x80000006 |
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#define | PF_ARM_DSP 0x80000007 |
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#define | PF_ARM_MOVE_CP 0x80000008 |
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#define | PF_ARM_VFP10 0x80000009 |
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#define | PF_ARM_MPU 0x8000000A |
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#define | PF_ARM_WRITE_BUFFER 0x8000000B |
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#define | PF_ARM_MBX 0x8000000C |
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#define | PF_ARM_L2CACHE 0x8000000D |
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#define | PF_ARM_PHYSICALLY_TAGGED_CACHE 0x8000000E |
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#define | PF_ARM_VFP_SINGLE_PRECISION 0x8000000F |
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#define | PF_ARM_VFP_DOUBLE_PRECISION 0x80000010 |
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#define | PF_ARM_ITCM 0x80000011 |
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#define | PF_ARM_DTCM 0x80000012 |
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#define | PF_ARM_UNIFIED_CACHE 0x80000013 |
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#define | PF_ARM_WRITE_BACK_CACHE 0x80000014 |
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#define | PF_ARM_CACHE_CAN_BE_LOCKED_DOWN 0x80000015 |
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#define | PF_ARM_L2CACHE_MEMORY_MAPPED 0x80000016 |
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#define | PF_ARM_L2CACHE_COPROC 0x80000017 |
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#define | PF_ARM_THUMB2 0x80000018 |
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#define | PF_ARM_T2EE 0x80000019 |
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#define | PF_ARM_VFP3 0x8000001A |
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#define | PF_ARM_NEON 0x8000001B |
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#define | PF_ARM_UNALIGNED_ACCESS 0x8000001C |
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#define | PF_ARM_INTEL_XSCALE 0x80010001 |
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#define | PF_ARM_INTEL_PMU 0x80010002 |
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#define | PF_ARM_INTEL_WMMX 0x80010003 |
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#define | MAX_COMPUTERNAME_LENGTH 31 |
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#define | GetComputerName GetComputerNameA |
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#define | GetComputerNameEx GetComputerNameExA |
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#define | GetTickCount64 winpr_GetTickCount64 |
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#define | WINPR_TIME_NS_TO_S(ns) ((ns) / 1000000000ull) |
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#define | WINPR_TIME_NS_TO_MS(ns) ((ns) / 1000000ull) |
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#define | WINPR_TIME_NS_TO_US(ns) ((ns) / 1000ull) |
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#define | WINPR_TIME_NS_REM_NS(ns) ((ns) % 1000000000ull) |
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#define | WINPR_TIME_NS_REM_US(ns) (WINPR_TIME_NS_REM_NS(ns) / 1000ull) |
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#define | WINPR_TIME_NS_REM_MS(ns) (WINPR_TIME_NS_REM_US(ns) / 1000ull) |
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#define | PF_EX_LZCNT 1 |
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#define | PF_EX_3DNOW_PREFETCH 2 |
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#define | PF_EX_SSSE3 3 |
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#define | PF_EX_SSE41 4 |
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#define | PF_EX_SSE42 5 |
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#define | PF_EX_AVX 6 |
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#define | PF_EX_FMA 7 |
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#define | PF_EX_AVX_AES 8 |
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#define | PF_EX_AVX2 9 |
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#define | PF_EX_ARM_VFP1 10 |
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#define | PF_EX_ARM_VFP3D16 11 |
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#define | PF_EX_ARM_VFP4 12 |
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#define | PF_EX_ARM_IDIVA 13 |
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#define | PF_EX_ARM_IDIVT 14 |
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#define | PF_EX_AVX_PCLMULQDQ 15 |
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#define | PF_EX_AVX512F 16 |
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#define | PF_SSE_INSTRUCTIONS_AVAILABLE PF_XMMI_INSTRUCTIONS_AVAILABLE |
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#define | PF_SSE2_INSTRUCTIONS_AVAILABLE PF_XMMI64_INSTRUCTIONS_AVAILABLE |
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